Output Process of Variable Bit-Rate Flows in On-Chip Networks Based on Aggregate Scheduling
2011 (English)In: Proceedings of the International Conference on Computer Design, 2011, 445-446 p.Conference paper (Refereed)
In NoCs often several flows are merged into one aggregate flow due to heavy resource sharing. For strengthening formal performance analysis, we propose an improved model for an output flow of a FIFO multiplexer under aggregate scheduling. The model of the aggregate flow is formally proven and can serve as the basis for a stringent worst case delay and buffer analysis.
Place, publisher, year, edition, pages
2011. 445-446 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63676DOI: 10.1109/ICCD.2011.6081442ISI: 000298257400076ScopusID: 2-s2.0-83455244341ISBN: 978-1-4577-1952-3OAI: oai:DiVA.org:kth-63676DiVA: diva2:482680
IEEE 29th International Conference on Computer Design (ICCD)
Key: Nostrum. QC 201202012012-01-242012-01-242015-03-10Bibliographically approved