Network Calculus Applied to Verification of Memory Access Performance in SoCs
2007 (English)In: Proceedings of the 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007, 2007, 21-26 p.Conference paper (Refereed)
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of a SoC under design hard to predict. Network calculus defines the concept of flow and has been successfully used to analyse the performance of communication networks. We propose to apply network calculus to the verification of memory access latencies. Two novel network elements, packet stretcher and packet compressor, are used to model the SoC interconnect and DRAM controller. We further extend the flow concept with a degree and make use of the peak characteristics of a flow to tighten the bounds in the analysis. We present a video playback case study and show that the proposed application of network calculus allows us to statically verify that all requirements on memory access latency are fulfilled.
Place, publisher, year, edition, pages
2007. 21-26 p.
Calculations, Computer programming languages, Dynamic random access storage, Embedded systems, Functions, Integrated circuits, Multimedia systems, Ports and harbors, Programmable logic controllers, Real time systems, Technical presentations
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63669DOI: 10.1109/ESTMED.2007.4375796ISI: 000253271600003ScopusID: 2-s2.0-47849101627ISBN: 978-142441654-7OAI: oai:DiVA.org:kth-63669DiVA: diva2:482681
2007 5th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007; Salzburg; Austria; 4 October 2007 through 5 October 2007
QC 201202022012-01-242012-01-242014-11-07Bibliographically approved