Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early-Chip Planning
2011 (English)In: 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011, 310-317 p.Conference paper (Refereed)
Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.
Place, publisher, year, edition, pages
2011. 310-317 p.
Computational modeling, Integrated circuit modeling, Program processors, Random access memory, System-on-a-chip, Topology, Wires
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63657DOI: 10.1109/ICCAD.2011.6105347ScopusID: 2-s2.0-84855811842ISBN: 978-1-4577-1398-9ISBN: 978-1-4577-1399-6OAI: oai:DiVA.org:kth-63657DiVA: diva2:482739
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
QC 201201252012-01-242012-01-242012-01-25Bibliographically approved