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3-D Integration and the Limits of Silicon Computation
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2011 (English)In: Proceedings of the International Conference on Very Large Scale Integration (VLSI-SoC), 2011, 343-348 p.Conference paper, Published paper (Refereed)
Abstract [en]

The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use the ECE and ECD to study the limits of performance under different memory distribution, power, thermal and cost constraints for various 2-D and 3-D topologies, in current and future technology nodes.

Place, publisher, year, edition, pages
2011. 343-348 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63656DOI: 10.1109/VLSISoC.2011.6081605Scopus ID: 2-s2.0-83755172185OAI: oai:DiVA.org:kth-63656DiVA: diva2:482742
Conference
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011. Kowloon. 3 October 2011 - 5 October 2011
Note
QC 20120124Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2012-01-24Bibliographically approved

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