Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique
2010 (English)In: Proceedings of the IEEE Annual Symposium on VLSI, 2010, 462-463 p.Conference paper (Refereed)
This paper explores a dynamic buffer allocation technique to guide a distributedsynchronization architecture to support efficient synchronization on multi-core Network-on-Chips (NoCs). The synchronization architecture features two physical buffers to be able to concurrently queue and handle synchronization requests issued by the local processor and remote processors via the on-chip network. Using the dynamic bufferallocation technique, the two physical buffers are dynamically allocated to form multiple virtual buffers in order to improve buffers' utilization. Experiments are carried on to evaluate buffers' utilization.
Place, publisher, year, edition, pages
2010. 462-463 p.
Distributed synchronization, Dynamic buffer allocation, Multi core, On-chip networks, Remote processors
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63634DOI: 10.1109/TSVLSI.2010.16ScopusID: 2-s2.0-77957901439ISBN: 978-076954076-4OAI: oai:DiVA.org:kth-63634DiVA: diva2:482823
IEEE Annual Symposium on VLSI, ISVLSI 2010, Lixouri, Kefalonia, 5 July 2010 through 7 July 2010
Key: Nostrum. QC 201202092012-01-242012-01-242012-02-09Bibliographically approved