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Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2010 (English)In: Proceedings of the IEEE Annual Symposium on VLSI, 2010, 462-463 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper explores a dynamic buffer allocation technique to guide a distributedsynchronization architecture to support efficient synchronization on multi-core Network-on-Chips (NoCs). The synchronization architecture features two physical buffers to be able to concurrently queue and handle synchronization requests issued by the local processor and remote processors via the on-chip network. Using the dynamic bufferallocation technique, the two physical buffers are dynamically allocated to form multiple virtual buffers in order to improve buffers' utilization. Experiments are carried on to evaluate buffers' utilization.

Place, publisher, year, edition, pages
2010. 462-463 p.
Keyword [en]
Distributed synchronization, Dynamic buffer allocation, Multi core, On-chip networks, Remote processors
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63634Scopus ID: 2-s2.0-77957901439OAI: oai:DiVA.org:kth-63634DiVA: diva2:482823
Conference
IEEE Annual Symposium on VLSI, ISVLSI 2010, Lixouri, Kefalonia, 5 July 2010 through 7 July 2010
Note

Key: Nostrum. QC 20120209

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2017-06-13Bibliographically approved

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Other links

Scopushttp://web.it.kth.se/~axel/papers/2010/ISVLSI-XiaowenChen.pdf

Authority records BETA

Lu, Zhonghai

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