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Handling Shared Variable Synchronization in Multi-core Network-on-Chips with Distributed Memory
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2010 (English)In: Proceedings: IEEE International SOC Conference, SOCC 2010, 2010, 467-472 p.Conference paper, Published paper (Refereed)
Abstract [en]

Parallelized shared variable applications running on multi-core Network-on-Chips(NoCs) require efficient support for synchronization, since communication is on the critical path of system performance and contended synchronization requests may cause large performance penalty. In this paper, we propose a dedicated hardware module forsynchronization management. This module is called Synchronization Handler (SH), integrated with each processor-memory node on the multi-core NoCs. It uses two physical buffers to concurrently process synchronization requests issued by the local processor and remote processors via the on-chip network. One salient feature is that the two physical buffers are dynamically allocated to form multiple virtual buffers (a virtual buffer is related to a shared synchronization variable) so as to improve the buffer utilization and alleviate the head-of-line blocking. Synthesis results suggest that the SH can run over 900 MHz in 130nm technology with small area overhead. To justify the SH-enhanced multicore NoCs, we employ synthetic workloads to evaluate synchronizationcost and buffer utilization, and run synchronization-intensive applications to investigate speedup. The results show that our approach is viable.

Place, publisher, year, edition, pages
2010. 467-472 p.
Keyword [en]
900 MHz, Buffer utilization, Critical Paths, Dedicated hardware, Distributed Memory, Head of line blocking, Multi core, Network-on-chips, On-chip networks, Performance penalties, Process synchronization, Processor-memory, Remote processors, Salient features, Shared variables, Small area, Synchronization cost, Synthetic workloads
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63635DOI: 10.1109/SOCC.2010.5784680Scopus ID: 2-s2.0-79960729241ISBN: 978-142446683-2 (print)OAI: oai:DiVA.org:kth-63635DiVA: diva2:482825
Conference
23rd IEEE International SOC Conference, SOCC 2010, Las Vegas, NV, 27 September 2010 through 29 September 2010
Note
Key: Nostrum. QC 20120209Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2012-02-09Bibliographically approved

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Publisher's full textScopushttp://web.it.kth.se/~axel/papers/2010/SOCC-XiaowenChen.pdf

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Lu, Zhonghai

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