A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip
2012 (English)In: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E95D, no 5, 1519-1522 p.Article in journal (Refereed) Published
In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 7 x 7 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.
Place, publisher, year, edition, pages
2012. Vol. E95D, no 5, 1519-1522 p.
3D NoC, bufferless router, permutation network
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63636DOI: 10.1587/transinf.E95.D.1519ISI: 000304573100036ScopusID: 2-s2.0-84860606209OAI: oai:DiVA.org:kth-63636DiVA: diva2:482835
QC 201206252012-01-242012-01-242012-06-25Bibliographically approved