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Mapping Optimisation for Scalable multi-core ARchiTecture: The MOSART approach
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2010 (English)In: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, 518-523 p.Conference paper (Refereed)
Abstract [en]

The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.

Place, publisher, year, edition, pages
2010. 518-523 p.
Keyword [en]
Data structures, Middleware, VLSI circuits
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-63629DOI: 10.1109/ISVLSI.2010.71ScopusID: 2-s2.0-77957909715ISBN: 978-076954076-4OAI: diva2:482837
IEEE Annual Symposium on VLSI, ISVLSI 2010. Lixouri, Kefalonia. 5 July 2010 - 7 July 2010

QC 20120201

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2016-07-22Bibliographically approved

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Lu, ZhonghaiChen, XiaowenChabloz, Jean-MichelHemani, AhmedJantsch, Axel
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ReferencesLink to record
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