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Multi-FPGA Implementation of a Network-on-Chip Based Many-core Architecture with Fast Barrier Synchronization Mechanism
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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2010 (English)In: Proceedings of the IEEE Norchip Conference, 2010Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we propose a fast barrier synchronization mechanism, targetingNetwork-on-Chip based manycore architectures. Its salient feature is that, once thebarrier condition is reached, the "barrier release" acknowledgement is routed to all processor nodes in a broadcast way in order to save area by avoiding storing source node information and to minimize completion time by eliminating serialization of barrierreleasing. Then, we construct a multi-FPGA platform using Xilinx® Virtex 5 as FPGA chipsand implement a NoC based many-core architecture on it. FPGA utilization and simulation results show that our mechanism demonstrates both area and performance advantages over the barrier synchronization counterpart with unicast barrier releasing. 

Place, publisher, year, edition, pages
2010.
Keyword [en]
Barrier synchronization, Completion time, FPGA chips, Many-core architecture, Multi-FPGA, Network on chip, Processor nodes, Salient features, Simulation result, Source nodes, Unicast
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63631DOI: 10.1109/NORCHIP.2010.5669430Scopus ID: 2-s2.0-78751525896ISBN: 978-142448973-2 (print)OAI: oai:DiVA.org:kth-63631DiVA: diva2:482840
Conference
28th Norchip Conference, NORCHIP 2010, Tampere, 15 November 2010 through 16 November 2010
Note
Key: Nostrum. QC 20120209Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2012-02-09Bibliographically approved

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Publisher's full textScopushttp://web.it.kth.se/~axel/papers/2010/Norchip-XiaowenChen.pdf

Authority records BETA

Lu, Zhonghai

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CiteExportLink to record
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Citation style
  • apa
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