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Run-time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2010 (English)In: The 3rd IEEE International Symposium on Parallel Architectures, Algorithms and Programming (PAAP 2010), 2010, 39-46 p.Conference paper, Published paper (Refereed)
Abstract [en]

On multi-core Network-on-Chips (NoCs), mem- ories are preferably distributed and supporting Distributed Shared Memory (DSM) is essential for the sake of reusing huge amount of legacy code and easy programming. However, the DSM organization imports the inherent overhead of translating virtual memory addresses into physical memoryaddresses, resulting in negative performance. We observe that, in parallel applications, different data have different properties (private or shared). For the private data accesses, it's unnecessary to perform Virtual-to-Physical address translations. Even for the same datum, its property may be changeable in different phases of the program execution. Therefore, this paper focuses on decreasing the overhead of Virtual-to-Physical address translation and hence improving the system performance by introducing hybrid DSM organization and supporting run-time partitioning according to the data property. Thehybrid DSM organization aims at supporting fast and physical memory accesses for private data and maintaining a global and single virtual memory space for shared data. Based on the data property of parallel applications, the run-time partitioning supports changing the hybrid DSM organization during the program execution. It ensures fast physical memory addressing on private data and conventional virtual memory addressingon shared data, improving the performance of the entire system by reducing virtual-to-physical address translation overhead as much as possible. We formulate the run-timepartitioning of hybrid DSM organization in order to analyze its perfor- mance. A real DSM based multi-core NoC platform is also constructed. The experimental results of real applications show that the hybrid DSM organization with run-time partitioningdemonstrates performance advantage over the conventional DSM counterpart. The percentage of performance improve- ment depends on problem size, way of datapartitioning and computation/ communication ratio of parallel applications, network size of the system, etc. In our experiments, the maximal improvement is 34.42%, the minimal improvement 3.68%.

Place, publisher, year, edition, pages
2010. 39-46 p.
Keyword [en]
Hybrid distributed shared memory (DSM), Multi-core, Network-on-Chips (NoCs), Run-time partitioning
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63632DOI: 10.1109/PAAP.2010.21Scopus ID: 2-s2.0-79952570435ISBN: 978-076954312-3 (print)OAI: oai:DiVA.org:kth-63632DiVA: diva2:482841
Conference
3rd International Symposium on Parallel Architectures, Algorithms and Programming, PAAP 2010, Dalian, 18 December 2010 through 20 December 2010
Note

Key: Nostrum. QC 20120209

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2013-09-06Bibliographically approved

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Publisher's full textScopushttp://web.it.kth.se/~axel/papers/2010/PAAP-XiaowenChen.pdf

Authority records BETA

Lu, Zhonghai

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CiteExportLink to record
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Citation style
  • apa
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