Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling
2012 (English)In: Proceedings of the Design and Test in Europe Conference (DATE), 2012, 538-541 p.Conference paper (Refereed)
Aggregate scheduling in routers merges several flows into one aggregate flow. We propose an approach for computing the end-to-end delay bound of individual flows in a FIFO multiplexer under aggregate scheduling. A synthetic case study exhibits that the end-to-end delay bound is up to 33.6% tighter than the case without considering the traffic peak behavior.
Place, publisher, year, edition, pages
2012. 538-541 p.
, Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
Delay analysis, End-to-end delay bounds, Network on chip, Variable bit rate
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63611ScopusID: 2-s2.0-84862080160ISBN: 978-398108018-6OAI: oai:DiVA.org:kth-63611DiVA: diva2:482859
15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012; Dresden; Germany; 12 March 2012 through 16 March 2012
QC 201309122012-01-242012-01-242015-03-10Bibliographically approved