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Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
2012 (English)In: Proceedings of the Design and Test in Europe Conference (DATE), 2012, 538-541 p.Conference paper, Published paper (Refereed)
Abstract [en]

Aggregate scheduling in routers merges several flows into one aggregate flow. We propose an approach for computing the end-to-end delay bound of individual flows in a FIFO multiplexer under aggregate scheduling. A synthetic case study exhibits that the end-to-end delay bound is up to 33.6% tighter than the case without considering the traffic peak behavior.

Place, publisher, year, edition, pages
2012. 538-541 p.
Series
Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
Keyword [en]
Delay analysis, End-to-end delay bounds, Network on chip, Variable bit rate
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63611Scopus ID: 2-s2.0-84862080160ISBN: 978-398108018-6 (print)OAI: oai:DiVA.org:kth-63611DiVA: diva2:482859
Conference
15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012; Dresden; Germany; 12 March 2012 through 16 March 2012
Note

QC 20130912

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2015-03-10Bibliographically approved
In thesis
1. Analysis and Management of Communication in On-Chip Networks
Open this publication in new window or tab >>Analysis and Management of Communication in On-Chip Networks
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Regarding the needs of low-power, high-performance embedded systems and the growing computation-intensive applications, the number of computing resources in a single chip has enormously increased. The current VLSI technology is able to support such an integration of transistors and add many computing resources such as CPU, DSP, specific IPs, etc to build a Systemon- Chip (SoC). However, interconnection between resources becomes another challenging issue which can be raised by using an on-chip interconnection network or Network-on-Chip (NoC). NoC-based communication which allows pipelined concurrent transmissions of transactions is becoming a dominate infrastructure for many core computing platforms.

This thesis analyzes and manages both Best Effort (BE) and Guaranteed Service (GS) communications using analytical performance approaches. As the first step, the present thesis focuses on the flow control for BE traffic in NoC. It models BE source rates as the solution to a utility-based optimization problem which is constrained with link capacities while preserving GS traffic requirements at the desired level. Towards this, several utility functions including proportionally-fair, rate-sum, and max-min fair scenarios are investigated. Moreover, it is worth looking into a scenario in which BE source rates are determined in favor of minimizing the delay of such traffics. The presented flow control algorithms solve the proposed optimization problems determining injection rate in each BE source node.

In the next step, real-time systems with guaranteed service are considered. Real-time applications require performance guarantees even under worst-case conditions, i.e. Quality of Service (QoS). Using network calculus, we present and prove the required theorems for deriving performance metrics and then apply them to propose formal approaches for the worst-case performance analysis. The proposed analytical model is used to minimize total cost in the networks in terms of buffer and delay. To this end, we address several optimization problems and solve them to consider the impact of various objective functions. We also develop a tool which derives performance metrics for a given NoC, formulates and solves the considerable optimization problems to provide an invaluable insight for NoC designers.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xxi, 59 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 15:01
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-161178 (URN)978-91-7595-458-5 (ISBN)
Public defence
2015-03-30, Sal/hall C, Elektrum , KTH-ICT, Isafjordsgatan, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20150310

Available from: 2015-03-10 Created: 2015-03-09 Last updated: 2015-03-10Bibliographically approved

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Lu, Zhonghai

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