An Analytical Latency Model for Networks-on-Chip
2013 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 21, no 1, 113-123 p.Article in journal (Refereed) Published
We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). The proposed model takes as input an application communication graph, a topology graph, a mapping vector, and a routing matrix, and estimates average packet latency and router blocking time. It works for arbitrary network topology with deterministic routing under arbitrary traffic patterns. This model can estimate per-flow average latency accurately and quickly, thus enabling fast design space exploration of various design parameters in NoC designs. Experimental results show that the proposed analytical model can predict the average packet latency more than four orders of magnitude faster than an accurate simulation, while the computation error is less than 10% in non-saturated networks for different system-on-chip platforms.
Place, publisher, year, edition, pages
2013. Vol. 21, no 1, 113-123 p.
Modeling and prediction, network-on-chip (NoC), performance analysis and design aids, queueing theory
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63609DOI: 10.1109/TVLSI.2011.2178620ISI: 000312835000011ScopusID: 2-s2.0-84871803176OAI: oai:DiVA.org:kth-63609DiVA: diva2:482864
QC 201302042012-01-242012-01-242013-12-05Bibliographically approved