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Parallel Probing: Dynamic and constant time setup procedure in circuit switching NoC
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0001-7966-6128
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0061-3475
2012 (English)In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, IEEE Computer Society, 2012, 1289-1294 p.Conference paper (Refereed)
Abstract [en]

We propose a circuit switching Network-on-chip with a parallel probe searching setup method, which can search the entire network in constant time, only dependent on the network size but independent of the network load. Under a specific search policy, the setup procedure is guaranteed to terminate in time 3D+6 cycles, where D is the geometric distance between source and destination. If a path can be found, the method succeeds in 3D+6 cycles; if a path cannot be found, it fails in maximum 3D+6 cycles. Compared to previous work, our method can reduce the setup time and enhance the success rate of setups. Our experiments show that compared with a sequential probe searching method, this method can reduce the search time by up to 20%. Compared with a centralized channel allocator method, this method can enhance the success rate by up to 20%.

Place, publisher, year, edition, pages
IEEE Computer Society, 2012. 1289-1294 p.
, Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
Keyword [en]
Allocators, Circuit switching, Constant time, Geometric distances, Network load, Network on chip, Network size, Parallel probing, Search time, Searching methods, Set-up time
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-63610DOI: 10.1109/DATE.2012.6176691ScopusID: 2-s2.0-84862111830ISBN: 978-398108018-6OAI: diva2:482866
15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012; Dresden; Germany; 12 March 2012 through 16 March 2012

QC 20130114

Available from: 2012-01-24 Created: 2012-01-24 Last updated: 2015-11-09Bibliographically approved
In thesis
1. New circuit switching techniques in on-chip networks
Open this publication in new window or tab >>New circuit switching techniques in on-chip networks
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Network on Chip (NoC) is proposed as a promising technology to address the communication challenges in deep sub-micron era. NoC brings network-based communication into the on-chip environment and tackles the problems like long wire complexities, bandwidth scaling and so on. After more than a decade's evolution and development, there are many NoC architectures and solutions available. Nevertheless, NoCs can be classi_ed into two categories: packet switched NoC and circuit switched NoC. In this thesis, targeting circuit switched NoC, we present our innovations and considerations on circuit switched NoCs in three areas, namely, connection setup method, time division multiplexing (TDM) technology and spatial division multiplexing (SDM) technology.

Connection setup technique deeply inuences the architecture and performance of a circuit switched NoC, since circuit switched NoC requires to set up connections before launching data transfer. We propose a novel parallel probe based method for dynamic distributed connection setup. This setup method on one hand searches all the possible minimal paths in parallel. On the other hand, it also has a mechanism to reduce resource occupation during the path search process by reclaiming redundant paths. With this setup method, connections are more likely to be established because of the exploration on the path diversity.

TDM based NoC constitutes a sub-category of circuit switched NoC. We propose a double time-wheel technique to facilitate a probe based connection setup in TDM NoCs. With this technique, path search algorithms used in connection setup are no longer limited to deterministic routing algorithms. Moreover, the hardware cost can be reduced, since setup requests and data flows can co-exist in one network. Apart from the double time-wheel technique for connection setup, we also propose a highway technique that can enhance the slot utilization during data transfer. This technique can accelerate the transfer of a data flow while maintaining the throughput guarantee and the packet order.

SDM based NoC constitutes another sub-category of circuit switched NoC. SDM NoC can benefit from high clock frequency and simple synchronization efforts. To better support the dynamic connection setup in SDM NoCs, we design a single cycle allocator for channel allocation inside each router. This allocator can guarantee both strong fairness and maximal matching quality. We also build up a circuit switched NoC, which can support multiple channels and multiple networks, to study different ways of organizing channels and setting up connections. Finally, we make a comparison between circuit switched NoC and packet switched NoC. We show the strengths and weaknesses on each of them by analysis and evaluation.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. xvi, 82 p.
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 2015:18
National Category
Computer Systems
urn:nbn:se:kth:diva-176624 (URN)978-91-7595-727-2 (ISBN)
Public defence
2015-12-04, Sal A, Elektrum, KTH-ICT, Kista, 09:00 (English)

QC 20151109

Available from: 2015-11-09 Created: 2015-11-09 Last updated: 2015-11-09Bibliographically approved

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