Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Synchronization after design refinements with sensitive delay elements
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-4859-3100
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2007 (English)In: Proceedings of the International Conference on HW/SW Codesign and System Synthesis, 2007Conference paper, Published paper (Refereed)
Abstract [en]

The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at a high level of abstraction. In synchronous models, a local refinement increasing the delay in a single computation block may affect the functionality of the entire model. We provide a synchronization algorithm that preserves the system's functionality after design refinements, by using additional synchronization delays and making some delays sensitive to their input values. The refined and synchronized model stays latency equivalent to the original model. The advantages of our approach are the following: (a) we remain fully within the synchronous model of computation, (b) we preserve the functionality of the existing computation blocks, and (c) we do not require additional computation resources, specific communication protocols, wrapper circuits around computation blocks or schedulers.

Place, publisher, year, edition, pages
2007.
Keyword [en]
Design refinement, Synchronization, System design
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63913DOI: 10.1145/1289816.1289826Scopus ID: 2-s2.0-38849180905ISBN: 978-159593824-4 (print)OAI: oai:DiVA.org:kth-63913DiVA: diva2:483221
Conference
CODES+ISSS 2007: 5th International Conference on Hardware/Software Codesign and System Synthesis. Salzburg. 30 September 2007 - 3 October 2007
Note

QC 20120126

Available from: 2012-01-25 Created: 2012-01-24 Last updated: 2016-05-11Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Sander, Ingo

Search in DiVA

By author/editor
Raudvere, TarvoSander, IngoJantsch, Axel
By organisation
Electronic, Computer and Software Systems, ECS
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 21 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf