Using synchronizers for refining synchronous communication onto Hardware/Software architectures
2007 (English)In: RSP 2007: 18th IEEE/IFIP International Workshop on Rapid System Prototyping, Proceedings, IEEE Computer Society, 2007, 143-149 p.Conference paper (Refereed)
We have presented a formal set of synchronization components called synchronizers for refining synchronous communication onto HW/SW codesign architectures. Such an architecture imposes asynchronous communication between HW-HW SW-SW and HW-SW components. The synchronizers enable local synchronization, thus satisfy the synchronization requirement of a typical IP core. In this paper we present their implementations in HW, SW and HW/SW as well as their application. To validate our concepts, we conduct a case study on a Nios FPGA that comprises a processor memory and custom logic. The final HW/SW implementation achieves equivalent performance to pure HW implementation. Our prototyping experience suggests that the synchronizers can be standardized as library modules and effectively separate the design of computation from that of communication.
Place, publisher, year, edition, pages
IEEE Computer Society, 2007. 143-149 p.
, IEEE / IFIP International Symposium on Rapid System Prototyping. Proceedings, ISSN 1074-6005
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63868DOI: 10.1109/RSP.2007.38ISI: 000247659900021ScopusID: 2-s2.0-34548786731ISBN: 978-0-7695-2834-2OAI: oai:DiVA.org:kth-63868DiVA: diva2:483296
18th IEEE/IFIP International Workshop on Rapid System Prototyping, RSP '07; Porto alegre; 28 May 2007 through 30 May 2007
QC 201203022012-01-252012-01-242012-03-02Bibliographically approved