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Network-on Chip Micro-Benchmarks
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2008 (English)In: Embedded Systems Design, no SeptemberArticle in journal (Refereed) Published
Abstract [en]

The rapid development of Network-on-Chip (NoC) calls for a systematic approach to evaluate and fairly compare various NoC architectures. In this specification, we define a generic NoC architecture, a comprehensive set of synthetic workloads as micro-benchmarks, workload scenarios and evaluation criteria. These micro-benchmarks enable measuring particular properties of NoC architectures, complementing application benchmarks.

Place, publisher, year, edition, pages
2008. no September
Keyword [en]
Network-on-Chip, Performance Evaluation, Benchmark
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-63860OAI: oai:DiVA.org:kth-63860DiVA: diva2:483302
Note
Key: Nostrum. QC 20120408Available from: 2012-01-25 Created: 2012-01-24 Last updated: 2012-05-08Bibliographically approved

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No full text

Other links

http://www.embedded.com/design/multicore/210604311

Authority records BETA

Lu, Zhonghai

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