Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects
2011 (English)In: IET CIRC DEVICE SYST, ISSN 1751-858X, Vol. 5, no 6, 505-517 p.Article in journal (Refereed) Published
The authors present a performance boosting technique with a better power efficiency for delay-insensitive on-chip interconnects. The increase in signal propagation delay uncertainty with technology scaling makes self-timed delay-insensitive on-chip interconnects the most appropriate alternative. However, achieving high-performance communication in self-timed delay-insensitive links is difficult, especially for large bit parallel transmission because of the time-consuming detection of each bit validity. The authors present a high-speed completion detection technique along with its circuit implementation and two on-chip interconnects which use the proposed completion detection circuit. The performance, power consumption, power efficiency and area of the presented on-chip interconnects are analysed and compared with the conventionally implemented delay-insensitive interconnects. For 64-bit parallel transmission, 2.07 and 1.72 times throughput improvement with 47 and 39% more power efficiency have been achieved for the two interconnects compared to their conventional counterparts. The interconnect circuits are designed and simulated using Cadence Analog Spectre and Hspice with 65 nm complementary metal-oxide semiconductor technology from STMicroelectronics.
Place, publisher, year, edition, pages
2011. Vol. 5, no 6, 505-517 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-63277DOI: 10.1049/iet-cds.2010.0300ISI: 000298134800009ScopusID: 2-s2.0-82855161604OAI: oai:DiVA.org:kth-63277DiVA: diva2:483362
QC 201201252012-01-252012-01-232012-01-25Bibliographically approved