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Generation of Layouts from Circuit Schematics; A Graph Theoretic Approach2
KTH, School of Computer Science and Communication (CSC), Centres, Centre for High Performance Computing, PDC. (Parallelldatorcentrum)
1984 (English)Conference paper (Refereed)
Abstract [en]

A graph model is proposed to capture the topological properties of metal-oxide semiconductor (MOS) transistors and interconnections among transistors. A set of algorithms is devised for the enumeration of layout topologies of a circuit from its graph model. Layout topologies are presented in stick diagrams. The algorithms select a set of embedded layout topologies with the “fewest” number of jumpers for layout generation and compaction. Layouts for circuits with up to 36 transistors have been generated successfully. The layouts corresponding to the topologies generated and selected by the algorithms are, in most cases, smaller than compact hand layouts. The worst case computational complexity is O(n 2), where n is the number of transistors in the circuit.

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Computer and Information Science
URN: urn:nbn:se:kth:diva-65756DOI: 10.1145/317825.317831OAI: diva2:483648
The 1985 Design Automation Conference
NR 20140805Available from: 2012-01-25 Created: 2012-01-25Bibliographically approved

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Johnsson, Lennart
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