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The Promises and Limitations of 3-D Integration
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2011 (English)In: 3D Integration for NoC-based SoC Architectures, Springer Publishing Company, 2011, 27-44 p.Chapter in book (Other academic)
Abstract [en]

The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use ECE and ECD to study the limits of performance under different memory distribution constraints of various 2-D and 3-D topologies, in current and future technology nodes. Among other results, our model shows that in a 35 nm technology a 16 stack 3-D system can, as a theoretical upper limit, obtain 3.4 times the performance of a 2-D system (8.8 Tera OPS vs 2.6 TOPS) at 70% reduced frequency (2.1 vs 3.7 GHz) on 1/8 the total area (50 vs 400 mm2).

Place, publisher, year, edition, pages
Springer Publishing Company, 2011. 27-44 p.
Series
Integrated Circuits and Systems, Part 1
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-66361DOI: 10.1007/978-1-4419-7618-5_2OAI: oai:DiVA.org:kth-66361DiVA: diva2:483768
Note
QC 20120416Available from: 2012-01-25 Created: 2012-01-25 Last updated: 2012-04-16Bibliographically approved

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CiteExportLink to record
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  • apa
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Language
  • de-DE
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  • en-US
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  • Other locale
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Output format
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