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Mapping Packet Processing Applications on a Systolic  Array Network Processor
Politecnico di Torino, Italy.
Politecnico di Torino, Italy.
Politecnico di Torino, Italy.
KTH, School of Computer Science and Communication (CSC), Theoretical Computer Science, TCS.
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2008 (English)In: 2008 IEEE Workshop on High  Performance Switching and Routing (HPSR), Shanghai, China, IEEE , 2008, 30-37 p.Conference paper (Refereed)
Abstract [en]

Systolic array network processors represent an effective alternative to ASICs for the design of multi-gigabit packet switching and forwarding devices because of their flexibility, high aggregate throughput and deterministic worst-case performances. However such advantages come at the expense of some limitations, given both by the specific characteristics of the pipelined architecture and by the lack of support for portable high-level languages in the software development tools, forcing software engineers to deal with low level aspects of the underlying hardware platform. In this paper we present a set of techniques that have been implemented in the Network Virtual Machine (NetVM) compiler infrastructure for mapping general layer 2-3 packet processing applications on the Xelerated X11 systolic-array network processor. In particular we demonstrate that our compiler is able to effectively exploit the available hardware resources and to generate code that is comparable to hand-written one, hence ensuring excellent throughput performances.

Place, publisher, year, edition, pages
IEEE , 2008. 30-37 p.
National Category
Computer Science
URN: urn:nbn:se:kth:diva-66432ISI: 000265589000006ScopusID: 2-s2.0-60649088291ISBN: 978-1-4244-1981-4OAI: diva2:484018
2008 International Conference on High Performance Switching and Routing, HPSR 2008; Shanghai; 15 May 2008 through 17 May 2008
QC 20120306Available from: 2012-01-26 Created: 2012-01-26 Last updated: 2012-03-06Bibliographically approved

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