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Synthesis of parallel binary machines
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0001-7382-9408
2011 (English)In: Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on, 2011, 200-206 p.Conference paper (Refereed)
Abstract [en]

Binary machines are a generalization of Feedback Shift Registers (FSRs) in which both, feedback and feedforward, connections are allowed and no chain connection between the register stages is required. In this paper, we present an algorithm for synthesis of binary machines with the minimum number of stages for a given degree of parallelization. Our experimental results show that for sequences with high linear complexity such as complementary, Legendre, or truly random, parallel binary machines are an order of magnitude smaller than parallel FSRs generating the same sequence. The presented approach can potentially be of advantage for many applications including wireless communication, cryptography, and testing.

Place, publisher, year, edition, pages
2011. 200-206 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-62760DOI: 10.1109/ICCAD.2011.6105326ISI: 000299009100030ScopusID: 2-s2.0-84855794216ISBN: 978-1-4577-1398-9OAI: diva2:484520
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011
QC 20120130Available from: 2012-01-27 Created: 2012-01-20 Last updated: 2012-04-03Bibliographically approved

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Dubrova, Elena
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