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A Design Technique for High-Performance Self-Checking Combinational Circuits
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2001 (English)In: Proceedings of IEEE European Test Workshop, 2001, 11-15 p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
2001. 11-15 p.
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Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-62777OAI: oai:DiVA.org:kth-62777DiVA: diva2:484539
Note
NR 20140805Available from: 2012-01-27 Created: 2012-01-20 Last updated: 2012-01-27Bibliographically approved

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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
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Output format
  • html
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