Implementation of a scalable, globally plesiochronous locally synchronous, off-chip NoC communication protocol
2009 (English)In: 2009 NORCHIP, 2009, 1-5 p.Conference paper (Refereed)
Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance the NoC-grid off-chip is needed. In this paper, we present such a method. As a proof of concept, the protocol is implemented on a 4 by 4 Mesh NoC, with NIOS II CPU cores as nodes, partitioned across four separate Altera FPGA boards, each board hosting a Quad-Core (2x2) NoC, operating on a local 50 MHz clock. The inter-chip communication protocol uses asynchronous clock bridges, with a throughput of 50 Mbps (~1MFlit/s) and is completely scalable. The NoC has an onboard throughput of 650 Mbps (12.5 MFlit/s). Each Quad-Core uses 28% of the LUs, 18% of the ALUTs, 22 % of the dedicated registers and 31% of the total memory blocks of the Stratix II FPGAs. Application programs use an MPI compatible Hardware Abstraction Layer (HAL) to communicate with each other over the NoC.
Place, publisher, year, edition, pages
2009. 1-5 p.
IdentifiersURN: urn:nbn:se:kth:diva-66744DOI: 10.1109/NORCHP.2009.5397822ScopusID: 2-s2.0-77949601896ISBN: 978-142444310-9OAI: oai:DiVA.org:kth-66744DiVA: diva2:484592
2009 NORCHIP; Trondheim; 16 November 2009 through 17 November 2009
QC 201203072012-01-272012-01-272012-03-07Bibliographically approved