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Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0002-8072-1742
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-4859-3100
2009 (English)In: 6th FPGAworld Conference, Academic Proceedings 2009, ACM , 2009, 52-57 p.Conference paper, Published paper (Refereed)
Abstract [en]

The Multi-Core NoC is a 4 by 4 Mesh NoC targeted for Altera FPGAs. It implements a deflective routing policy and is used to connect sixteen NIOS II processors. Each NIOS II is connected to the NoC via an address-mapped Resource Network Interface. The Multi-Core NoC is implemented on four separate Altera Stratix II FPGA boards, each hosting a Quad-Core NoC, which operates on a local 50 MHz clock. It has an onboard throughput of 650 Mbps (12.5 MFlit/s), and uses 28% of the LUs, 18% of the ALUTs, 22 % of the dedicated registers and 31% of the total memory blocks of a Stratix II FPGA. Asynchronous clock bridges, with a throughput of 50 Mbps (∼1MFlit/s), are used for the inter-board communication. Application programs use an MPI compatible Hardware Abstraction Layer (HAL) to communicate with the Resource Network Interface of the NoC. The RNI sets up message transfer, with a maximum length of 512 bytes, and sends flits with the size of 32 bit data plus 20 bit headers through the network. The MPI is the bottleneck of the system; it takes 46 us (43.4 kPackets/s) to send a minimum-sized packet through the protocol stack to a near neighbour and bounce it back to the original application. The bounce-back time for a far neighbour is 56 us.

Place, publisher, year, edition, pages
ACM , 2009. 52-57 p.
Keyword [en]
Altera, FPGA, Hardware platform, MPI, MPSoC, Multi-core, NoC, Plesiochronous
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-66684DOI: 10.1145/1667520.1667527Scopus ID: 2-s2.0-76749095935ISBN: 978-160558879-7 (print)OAI: oai:DiVA.org:kth-66684DiVA: diva2:484593
Conference
6th FPGAworld Conference, FPGAworld 2009; Stockholm; 10 September 2009 through 10 September 2009
Note
QC 20120301Available from: 2012-01-27 Created: 2012-01-27 Last updated: 2012-03-01Bibliographically approved

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