Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
2009 (English)In: ACM Trans. Reconfigurable Technol. Syst., ISSN 1936-7406, Vol. 2, no 2, 1-36 p.Article in journal (Refereed) Published
Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In theory, the compressor trees contained within the multipliers could implement multi-input addition; however, they are not exposed to the programmer. To improve FPGA performance for these applications, this article introduces the Field Programmable Compressor Tree (FPCT) as an alternative to the DSP blocks. By providing just a compressor tree, the FPCT can perform multi-input addition along with parallel multiplication and MAC in conjunction with a small amount of FPGA general logic. Furthermore, the user can configure the FPCT to precisely match the bitwidths of the operands being summed. Although an FPCT cannot beat the performance of a well-designed ASIC compressor tree of fixed bitwidth, for example, 9Ã—9 and 18Ã—18-bit multipliers/MACs in DSP blocks, its configurable bitwidth and ability to perform multi-input addition is ideal for reconfigurable devices that are used across a variety of applications.
Place, publisher, year, edition, pages
2009. Vol. 2, no 2, 1-36 p.
compressor tree, field programmable compressor tree (fpct), field programmable gate array (fpga)
IdentifiersURN: urn:nbn:se:kth:diva-46480DOI: 10.1145/1534916.1534923ISI: 000208166500007ScopusID: 2-s2.0-77954282426OAI: oai:DiVA.org:kth-46480DiVA: diva2:484863
QC 201202022012-01-272011-11-032012-09-04Bibliographically approved