An 8-bit 166nw 11.25 kS/s 0.18um two-step-SAR ADC for RFID applications using novel DAC architecture
2010 (English)In: 28th Norchip Conference, NORCHIP 2010, 2010, 1-4 p.Conference paper (Refereed)
SAR ADCs have been mostly used for moderate-speed, moderate-resolution applications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC. In this paper an ultra low power two-step-SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with no static current and a dual-stage (Resistor-string / capacitive dividing) architecture as digital-to-analog converter (DAC). In this DAC architecture fine search will be performed by only two C and 15C capacitors which reduced the silicon area significantly. The circuit designed in 0.18um CMOS technology and simulations show that the 8-bit ADC, consumes almost 166nW at 11.25kS/s. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison with its charge redistribution counterpart.
Place, publisher, year, edition, pages
2010. 1-4 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-68809DOI: 10.1109/NORCHIP.2010.5669487ScopusID: 2-s2.0-78751513537ISBN: 978-142448973-2OAI: oai:DiVA.org:kth-68809DiVA: diva2:485342
28th Norchip Conference, NORCHIP 2010; Tampere; Finland; 15 November 2010 through 16 November 2010
QC 201507152012-01-282012-01-282015-07-15Bibliographically approved