The Design of All-Digital Polar Transmitter based on ADPLL and Phase Synchronized Delta Sigma Modulator
2012 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 47, no 5, 1154-1164 p.Article in journal (Refereed) Published
An improved architecture of polar transmitter (TX) is presented. The proposed architectureis digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phasemodulation, a 1-bit low-pass delta sigma (Delta Sigma) modulator for envelop modulation, and aH-bridge class-D power amplifier (PA) for differential signaling. The (Delta Sigma) modulator isclocked using the phase modulated RF carrier to ensure phase synchronization between theamplitude and phase path, and to guarantee the PA is switching at zero crossings of theoutput current.An on chip pre-filter is used to reduce the parasitic capacitance from packages at theswitch stage output. The high over sampling ratio of the (Delta Sigma) modulator move quantizationnoise far away from the carrier frequency, ensuring good in-band performance and relax filterrequirements. The on-chip filter also acts as impedance matching and differential to singleended conversion. The measured digital transmitter consumes 58 mW from a 1 V at 6.8 dBm output power.
Place, publisher, year, edition, pages
IEEE Solid-State Circuits Society, 2012. Vol. 47, no 5, 1154-1164 p.
All digital, polar transmitter, transmitter, ADPLL, Delta Sigma
IdentifiersURN: urn:nbn:se:kth:diva-72240DOI: 10.1109/JSSC.2012.2186720ISI: 000303329600010ScopusID: 2-s2.0-84860475717OAI: oai:DiVA.org:kth-72240DiVA: diva2:487338
FunderICT - The Next Generation
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QC 201205032012-05-032012-01-312013-04-11Bibliographically approved