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A reconfigurable processor for phylogenetic inference
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
Department of Computer Science and engineering, Indian Institute of Technology.
2011 (English)In: VLSI Design (VLSI Design), 2011 24th International Conference on, IEEE , 2011, 226-231 p.Conference paper, Published paper (Refereed)
Abstract [en]

A reconfigurable processor tailored for accelerating Phylogenetic Inference is proposed. In this paper, a programmable and scalable architectural platform instantiates an array of coarse grained light weight processing elements, which allows arbitrary partitioning, scheduling schemes and capable of solving complete Maximum Likelihood algorithm with arbitrarily of large sequences. The key difference of the proposed CGRA based solution compared to FPGA and GPU based solutions is a much better match of the architecture and algorithm for the core computational need as well as the system level architectural need. For the same degree of parallelism, we provide a 2.27X speed-up improvements compared to FPGA with the same amount of logic, and an 81.87X speed-up improvements compared to GPU with the same silicon area respectively.

Place, publisher, year, edition, pages
IEEE , 2011. 226-231 p.
Series
International Conference on VLSI Design. Proceedings, ISSN 1063-9667 ; 2011
Keyword [en]
Phylogenetic Inference, Maximum Likelihood Algorithm, Phylogenetic Likelihood Function, Coarse Grain Reconfigurable Architecture, VLSI
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73028DOI: 10.1109/VLSID.2011.74Scopus ID: 2-s2.0-79952857602ISBN: 978-0-7695-4348-2 (print)ISBN: 978-1-61284-327-8 (print)OAI: oai:DiVA.org:kth-73028DiVA: diva2:488498
Conference
24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems; Chennai; 2 January 2011 through 7 January 2011
Note
QC 20120221Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-21Bibliographically approved

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Hemani, Ahmed

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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf