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High level synthesis in DSP ASIC optimization
Tampere University of Technology, Signal Processing Laboratory.
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0002-8072-1742
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0003-0565-9376
KTH, Superseded Departments, Electronic Systems Design.
1994 (English)In:  Proc. of 7th IEEE ASIC Conference and Exhibit, 1994, 75-78 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples

Place, publisher, year, edition, pages
1994. 75-78 p.
Keyword [en]
DSP ASIC optimization; Matlab; SYNT synthesis tools; Synopsys synthesis tools; behavioural VHDL description; coefficient optimization; digital signal processing; high level synthesis; multiply-accumulate based FIR filters; power-of-two FIR filters; rule based preallocator; FIR filters; application specific integrated circuits; circuit optimisation; digital filters; digital signal processing chips; high level synthesis;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73086DOI: 10.1109/ASIC.1994.404605OAI: oai:DiVA.org:kth-73086DiVA: diva2:488512
Conference
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Note
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-17Bibliographically approved

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Öberg, JohnnyHemani, Ahmed

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