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HLS based DSP optimization with ASIC RTL libraries
Tampere University of Technology, Signal Processing Laboratory.
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0002-8072-1742
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0003-0565-9376
KTH, Superseded Departments, Electronic Systems Design.
1994 (English)In:  , 1994, 218-225 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we show how the High Level Synthesis (HLS) tool can efficiently be used for DSP ASIC development. The performance of general HLS tool is improved with simple transformations and code optimizations, and a direct mapping to technology optimized parameterizable ASIC Register Transfer Level (RTL) library. The library mapping contains three phases: a structure recognition, an architecture selection and a parameter optimization. As an optimization framework SYNT, Synopsys and Matlab design environments are integrated. Lsi10k and Xilinx 4000 series are used as target technologies to demonstrate the performance of the approach

Place, publisher, year, edition, pages
1994. 218-225 p.
Keyword [en]
ASIC RTL libraries; ASIC development; DSP optimization; Lsi10k series; Matlab; SYNT; Synopsys; Xilinx 4000 series; architecture selection; code optimizations; design environments; high level synthesis; parameter optimization; register transfer level; structure recognition; high level synthesis;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73083DOI: 10.1109/VLSISP.1994.574746OAI: oai:DiVA.org:kth-73083DiVA: diva2:488516
Conference
VLSI Signal Processing, VII, 1994., [Workshop on]
Note
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-17Bibliographically approved

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Öberg, JohnnyHemani, Ahmed

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