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Application of high-level synthesis in an industrial project
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0003-0565-9376
Bofors AB Missiles.
Synthesia AB.
Synthesia AB.
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1994 (English)In: VLSI Design, 1994., Proceedings of the Seventh International Conference on, 1994, 5-10 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes the use of high-level synthesis in conjunction with logic synthesis for designing an industrial product specified at system-level in behavioral VHDL and realized in FPGAs. The designers’ experiences from using the high-level synthesis tool and its interaction with the other tools are analyzed. Important problems were the handling of precise timing constraints and feedback of adequate technology information to the high-level synthesis

Place, publisher, year, edition, pages
1994. 5-10 p.
Keyword [en]
FPGA;behavioral VHDL;high-level synthesis tool;industrial project;logic synthesis;precise timing constraints;system-level;technology information feedback;circuit CAD;logic CAD;logic arrays;software tools;specification languages;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73081DOI: 10.1109/ICVD.1994.282639OAI: oai:DiVA.org:kth-73081DiVA: diva2:488520
Conference
VLSI Design, 1994.
Note
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-17Bibliographically approved

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Hemani, Ahmed

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