Application of high-level synthesis in an industrial project
1994 (English)In: VLSI Design, 1994., Proceedings of the Seventh International Conference on, 1994, 5-10 p.Conference paper (Refereed)
This paper describes the use of high-level synthesis in conjunction with logic synthesis for designing an industrial product specified at system-level in behavioral VHDL and realized in FPGAs. The designers’ experiences from using the high-level synthesis tool and its interaction with the other tools are analyzed. Important problems were the handling of precise timing constraints and feedback of adequate technology information to the high-level synthesis
Place, publisher, year, edition, pages
1994. 5-10 p.
FPGA;behavioral VHDL;high-level synthesis tool;industrial project;logic synthesis;precise timing constraints;system-level;technology information feedback;circuit CAD;logic CAD;logic arrays;software tools;specification languages;
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-73081DOI: 10.1109/ICVD.1994.282639OAI: oai:DiVA.org:kth-73081DiVA: diva2:488520
VLSI Design, 1994.
NR 201408052012-02-012012-02-012012-02-17Bibliographically approved