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Exploiting data transfer locality in memory mapping
KTH, School of Information and Communication Technology (ICT).
IMEC.
IMEC, Katholieke Universiteit.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
1999 (English)In: EUROMICRO Conference, 1999. Proceedings. 25th, 1999, Vol. 1, 14-21 p.Conference paper, Published paper (Refereed)
Abstract [en]

System-level exploration of memory architectures is one of the key issues in successful implementation of data-transfer dominated applications. Usually, one of the main design bottlenecks is the memory access bandwidth. Transformations, rearranging the layout of the data records stored in memory, are very effective to improve the locality of the data transfers but usually lead to a large memory bit-wastage when not performed carefully. In this paper, a methodology which reduces memory bandwidth requirements without sacrificing storage space is proposed. The methodology exploits parallelism in the data-transfers to rearrange the layout of the data records. Distributed memory organization combined with our proposed layout rearrangement methodology allow to effectively reduce the memory bandwidth bottleneck in data-transfer dominated applications

Place, publisher, year, edition, pages
1999. Vol. 1, 14-21 p.
Keyword [en]
data transfer locality;memory access bandwidt;memory architectures;memory mapping;parallelism;storage space;data structures;memory architecture;parallel architectures;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73120DOI: 10.1109/EURMIC.1999.793132OAI: oai:DiVA.org:kth-73120DiVA: diva2:488546
Note
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-01Bibliographically approved

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