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Globally asynchronous locally synchronous architecture for large high-performance ASICs
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT).
KTH, School of Information and Communication Technology (ICT).
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1999 (English)In:  , 1999, Vol. 2, 512-515 p.Conference paper, Published paper (Refereed)
Abstract [en]

Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%

Place, publisher, year, edition, pages
1999. Vol. 2, 512-515 p.
Keyword [en]
0.25 micron;20 MHz to 1 GHz;clock nets;communication overhead;design bottleneck;globally asynchronous locally synchronous architecture;handshake protocols;handshake signals;high-performance ASICs;net power savings;operating frequencies;partitioning method;power consumption;tolerable clock skew;VLSI;application specific integrated circuits;asynchronous circuits;circuit CAD;clocks;integrated circuit design;logic CAD;logic partitioning;protocols;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73119DOI: 10.1109/ISCAS.1999.780794OAI: oai:DiVA.org:kth-73119DiVA: diva2:488549
Conference
Circuits and Systems, 1999. ISCAS ’99. Proceedings of the 1999 IEEE International Symposium on
Note
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-12Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
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  • de-DE
  • en-GB
  • en-US
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  • Other locale
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