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Lowering power consumption in clock by using globally asynchronous locally synchronous design style
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Indian Institute of Technology.
Department of CSEE, University of Queensland.
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1999 (English)In: Design Automation Conference, 1999. Proceedings. 36th, 1999, 873-878 p.Conference paper, Published paper (Refereed)
Abstract [en]

Power consumption in clock of large high performance VLSIs can be reduced by adopting globally asynchronous, locally synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to (a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and (b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads

Place, publisher, year, edition, pages
1999. 873-878 p.
Keyword [en]
GALS;globally asynchronous locally synchronous design style;high performance VLSIs;local clock generation;overheads;partitioning;power consumption;power saving;synchronous blocks;VLSI;application specific integrated circuits;clocks;integrated circuit design;logic CAD;logic partitioning;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73116DOI: 10.1109/DAC.1999.782202OAI: oai:DiVA.org:kth-73116DiVA: diva2:488553
Note
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-01Bibliographically approved

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