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System level virtual prototyping of DSP ASICs using grammar based approach
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Ericsson Radio Systems AB.
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1999 (English)In: Rapid System Prototyping, 1999. IEEE International Workshop on, 1999, 166-171 p.Conference paper, Published paper (Refereed)
Abstract [en]

DSP systems are often modeled using functional and bit-true level simulators, where it is not possible to validate the system level timing, control and configuration (SLTCC) of the product. In this paper, we present a methodology that adds SLTCC specified in grammar to functional models to create a rate true system level virtual prototype. The methodology is illustrated and benefits are quantified using two realistic examples

Place, publisher, year, edition, pages
1999. 166-171 p.
Keyword [en]
DSP ASICs;bit-true level simulators;control and configuration;grammar based approach;system level timing;system level virtual prototype;system level virtual prototyping;application specific integrated circuits;computational complexity;digital signal processing chips;software prototyping;timing;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73115DOI: 10.1109/IWRSP.1999.779048OAI: oai:DiVA.org:kth-73115DiVA: diva2:488556
Note
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-01Bibliographically approved

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CiteExportLink to record
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  • apa
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