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A digitally controlled on-chip clock multiplier for globally asynchronous locally synchronous systems
Dept. of Applied Electronics, Univ. of Lund.
Dept. of Applied Electronics, Univ. of Lund.
Dept. of Applied Electronics, Univ. of Lund.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
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1999 (English)In: Circuits and Systems, 1999. 42nd Midwest Symposium on, 1999, Vol. 1, 84-87 p.Conference paper, Published paper (Refereed)
Abstract [en]

For large high-speed globally synchronous ASICs, designing the clock distribution net becomes a troublesome task. Besides problems caused by clock skew, the clock net also is a major source of power consumption. Partitioning the design into locally clocked blocks reduces clock skew problems and if handled correctly it also helps reducing power consumption. However, to achieve these positive effects, the blocks need on-chip clocks having properties as small area and low power consumption. Therefore, a low power small area digitally controlled on-chip clock generator is designed

Place, publisher, year, edition, pages
1999. Vol. 1, 84-87 p.
Keyword [en]
clock distribution;clock skew;digital control;globally asynchronous locally synchronous system;high-speed ASIC;low-power design;on-chip clock multiplier;application specific integrated circuits;clocks;high-speed integrated circuits;low-power electronics;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73114DOI: 10.1109/MWSCAS.1999.867215OAI: oai:DiVA.org:kth-73114DiVA: diva2:488557
Note
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-01Bibliographically approved

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