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Test strategies on functionally partitioned module-based programmable architecture for base-band processing
Department of CSEE, University of Queensland.
Department of CSEE, University of Queensland.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0003-0565-9376
2001 (English)In: Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 2001, 326-333 p.Conference paper (Refereed)
Abstract [en]

A specialised reconfigurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing matrices is also minimised, which increases throughput without sacrificing flexibility. The testing algorithm was developed to systematically search for faults in the processing modules and the flexible high-speed routing network within the architecture. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This algorithm scans all possible paths within the interconnection network exhaustively and reports all faults. Strategies can be inserted to bypass minor faults

Place, publisher, year, edition, pages
2001. 326-333 p.
Keyword [en]
connecting buses;externally addressable memory space;flexible high-speed routing network;functionally partitioned module-based programmable architecture ;local switch matrix;master controller;processing modules;reconfigurable architecture;route-through switch matrix;routing matrices;routing network;shared memory;systematic fault searching;telecommunication base-band processing;test strategies;test vectors;virtual wire hardware modules;logic testing;multiprocessor interconnection networks;reconfigurable architectures;shared memory systems;telecommunication computing;telecommunication network routing;
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-73133DOI: 10.1109/DSD.2001.952317OAI: diva2:488566
Euromicro Symposium on Digital Systems, Design, 2001
NR 20140805Available from: 2012-02-01 Created: 2012-02-01 Last updated: 2012-02-17Bibliographically approved

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Hemani, Ahmed
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