Performance Analysis of 3D NoCs Partitioning Methods
2010 (English)In: IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, 479-480 p.Conference paper (Refereed)
3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with short vertical ones. Achieving higher performance along with reducing the network latency can be obtained by utilizing an efficient communication protocol in 3D Networks-on-Chlp (NoCs). In this work, several unlcast/multicast partitioning methods are explained in order to And an advantageous method with low communication latency. Moreover, two factors of efficiency, unicast latency and multicast latency, are analyzed by analytical models. We also perform simulation to compare the efficiency of proposed methods. The results show that Mixed Partitioning method outperforms other methods in term of latency.
Place, publisher, year, edition, pages
2010. 479-480 p.
3D IC design;3D NoC partitioning methods;communication protocol;low communication latency;mixed partitioning method;multicast latency;network latency;networks-on-chip;power consumption;unicast latency;unicast-multicast partitioning methods;integrated circuit design;network-on-chip;
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-73370DOI: 10.1109/ISVLSI.2010.26ScopusID: 2-s2.0-77957903603OAI: oai:DiVA.org:kth-73370DiVA: diva2:488832
IEEE Annual Symposium on VLSI, ISVLSI 2010. Lixouri, Kefalonia. 5 July 2010 - 7 July 2010
QC 201202082012-02-022012-02-022016-06-08Bibliographically approved