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Performance Analysis of 3D NoCs Partitioning Methods
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2010 (English)In: IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, 479-480 p.Conference paper, Published paper (Refereed)
Abstract [en]

3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with short vertical ones. Achieving higher performance along with reducing the network latency can be obtained by utilizing an efficient communication protocol in 3D Networks-on-Chlp (NoCs). In this work, several unlcast/multicast partitioning methods are explained in order to And an advantageous method with low communication latency. Moreover, two factors of efficiency, unicast latency and multicast latency, are analyzed by analytical models. We also perform simulation to compare the efficiency of proposed methods. The results show that Mixed Partitioning method outperforms other methods in term of latency.

Place, publisher, year, edition, pages
2010. 479-480 p.
Keyword [en]
3D IC design;3D NoC partitioning methods;communication protocol;low communication latency;mixed partitioning method;multicast latency;network latency;networks-on-chip;power consumption;unicast latency;unicast-multicast partitioning methods;integrated circuit design;network-on-chip;
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-73370DOI: 10.1109/ISVLSI.2010.26Scopus ID: 2-s2.0-77957903603OAI: oai:DiVA.org:kth-73370DiVA: diva2:488832
Conference
IEEE Annual Symposium on VLSI, ISVLSI 2010. Lixouri, Kefalonia. 5 July 2010 - 7 July 2010
Note

QC 20120208

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-06-08Bibliographically approved

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Citation style
  • apa
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  • nn-NB
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  • Other locale
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  • asciidoc
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