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Partitioning methods for unicast/multicast traffic in 3D NoC architecture
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2010 (English)In: Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, 2010, 127-132 p.Conference paper (Refereed)
Abstract [en]

As the scale of integration grows, the interconnection problem becomes one of the major design considerations of Multi Processor System on Chip (MPSoC). In recent years, many researchers have conducted studies on 3D IC designs stacking multiple layers on top of each other. In order to decrease the transmission delay of unicast/multicast messages in a network based multicore system, the network is divided into several partitions. In this paper, we first introduce a novel idea of balanced partitioning that allows the network to be partitioned effectively. Then, we propose a set of partitioning approaches each with a different level of efficiency. In addition, we present an advantageous method based on the idea of balanced partitioning to provide a high degree of parallelism with a considerable reduction of packet delay in unicast/multicast traffic. Simulations are provided to evaluate and compare the performance of proposed methods.

Place, publisher, year, edition, pages
2010. 127-132 p.
Keyword [en]
3D IC designs stacking multiple layers;3D NoC architecture;MPSoC;multiprocessor system on chip;network based multicore system;partitioning methods;unicast-multicast traffic;integrated circuit design;network-on-chip;telecommunication traffic;
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-73372DOI: 10.1109/DDECS.2010.5491800ScopusID: 2-s2.0-77954930025OAI: diva2:488834
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. Vienna. 14 April 2010 - 16 April 2010

QC 20120208

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-06-08Bibliographically approved

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Tenhunen, Hannu
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