Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Agent-based on-chip network using efficient selection method
Show others and affiliations
2011 (English)In: 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, IEEE , 2011, 284-289 p.Conference paper, Published paper (Refereed)
Abstract [en]

Congestion in on-chip networks may cause many drawbacks in multiprocessor systems including throughput reduction, increase in latency, and additional power consumption. Furthermore, conventional congestion control methods, employed for on-chip networks, cannot efficiently collect congestion information and distribute them over the on-chip network. In this paper, we present a novel structure for on-chip networks, named Agent-based Network-on-Chip (ANoC), to diagnose the congested areas. In addition to the presented structure, an efficient Congestion-Aware Selection (CAS) method is proposed to reduce overall network latency. CAS is capable of selecting an appropriate output channel to route packets along a less congested path. 29% average and 35% maximum latency reduction are achieved on SPLASH-2 and PARSEC benchmarks running on a 36-core Chip Multi-Processor.

Place, publisher, year, edition, pages
IEEE , 2011. 284-289 p.
Keyword [en]
PARSEC benchmarks;SPLASH-2;agent-based network-on-chip;congestion-aware selection;conventional congestion control methods;efficient selection method;latency;multiprocessor systems;on-chip networks;power consumption;multiprocessing systems;network-on-chip;power consumption;
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-73381DOI: 10.1109/VLSISoC.2011.6081593Scopus ID: 2-s2.0-83755163171OAI: oai:DiVA.org:kth-73381DiVA: diva2:488843
Conference
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011. Kowloon. 3 October 2011 - 5 October 2011
Note

QC 20120208

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-04-28Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Tenhunen, Hannu
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 27 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf