Efficient network interface architecture for network-on-chips
2009 (English)In: 2009 NORCHIP, 2009, 5397837Conference paper (Refereed)
In this paper, we present novel network interface architecture for on-chip networks to increase memory parallelism and to improve the resource utilization. The proposed architecture exploits AXI transaction based protocol to be compatible with existing IP cores. Experimental results with synthetic test case demonstrate that the proposed architecture outperforms the conventional architecture in term of latency.
Place, publisher, year, edition, pages
AXI transaction, memory parallelism, network interface architecture, network-on-chips, protocol, resource utilization, network interfaces, protocols
IdentifiersURN: urn:nbn:se:kth:diva-73374DOI: 10.1109/NORCHP.2009.5397837ScopusID: 2-s2.0-77949626883ISBN: 978-142444310-9OAI: oai:DiVA.org:kth-73374DiVA: diva2:488851
2009 NORCHIP. Trondheim. 16 November 2009 - 17 November 2009
QC 201202082012-02-022012-02-022016-07-22Bibliographically approved