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Efficient network interface architecture for network-on-chips
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2009 (English)In: 2009 NORCHIP, 2009, 5397837Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present novel network interface architecture for on-chip networks to increase memory parallelism and to improve the resource utilization. The proposed architecture exploits AXI transaction based protocol to be compatible with existing IP cores. Experimental results with synthetic test case demonstrate that the proposed architecture outperforms the conventional architecture in term of latency.

Place, publisher, year, edition, pages
2009. 5397837
Keyword [en]
AXI transaction, memory parallelism, network interface architecture, network-on-chips, protocol, resource utilization, network interfaces, protocols
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73374DOI: 10.1109/NORCHP.2009.5397837Scopus ID: 2-s2.0-77949626883ISBN: 978-142444310-9 (print)OAI: oai:DiVA.org:kth-73374DiVA: diva2:488851
Conference
2009 NORCHIP. Trondheim. 16 November 2009 - 17 November 2009
Note

QC 20120208

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-07-22Bibliographically approved

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