Change search
ReferencesLink to record
Permanent link

Direct link
Efficient network interface architecture for network-on-chips
Show others and affiliations
2009 (English)In: 2009 NORCHIP, 2009, 5397837Conference paper (Refereed)
Abstract [en]

In this paper, we present novel network interface architecture for on-chip networks to increase memory parallelism and to improve the resource utilization. The proposed architecture exploits AXI transaction based protocol to be compatible with existing IP cores. Experimental results with synthetic test case demonstrate that the proposed architecture outperforms the conventional architecture in term of latency.

Place, publisher, year, edition, pages
2009. 5397837
Keyword [en]
AXI transaction, memory parallelism, network interface architecture, network-on-chips, protocol, resource utilization, network interfaces, protocols
National Category
Computer Engineering
URN: urn:nbn:se:kth:diva-73374DOI: 10.1109/NORCHP.2009.5397837ScopusID: 2-s2.0-77949626883ISBN: 978-142444310-9OAI: diva2:488851
2009 NORCHIP. Trondheim. 16 November 2009 - 17 November 2009

QC 20120208

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-07-22Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Tenhunen, Hannu
By organisation
Electronic, Computer and Software Systems, ECS
Computer Engineering

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 39 hits
ReferencesLink to record
Permanent link

Direct link