Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers
2010 (English)In: Proceedings of the 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, ECBS 2010, IEEE , 2010, 131-138 p.Conference paper (Refereed)
Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput.
Place, publisher, year, edition, pages
IEEE , 2010. 131-138 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-73486DOI: 10.1109/ECBS.2010.21ScopusID: 2-s2.0-77953205609ISBN: 978-076954005-4OAI: oai:DiVA.org:kth-73486DiVA: diva2:488927
17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, ECBS 2010; Oxford; 22 March 2010 through 26 March 2010
QC 201202082012-02-022012-02-022016-05-09Bibliographically approved