Power- and performance-aware IP mapping for NoC-based MPSoC platforms
2010 (English)In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings, 2010, 758-761 p.Conference paper (Refereed)
In this paper, we address the performance of MPSoC platforms with homogeneous processing nodes, where the cores generate and consume the large amount of data, thus the system approaches congestion. Mostly, the time dependent media applications are time critical, where traffic must be delivered on time in order to operate properly. Proper task allocation or placement of IP cores at layout time is very important to meet such application requirements. Apart from meeting the application requirements, it also lowers the traffic congestion, power consumption and Average Packet Latency (APL). For task allocation or IP placement, the prioritization criteria has been proposed, which is used in next step to map the application on MPSoC platform. The proposed technique shows significant improvement in system performance and reduction in power consumption. To estimate the efficiency, the video conference encoding application and MPEG4 video encoder were mapped to 5x5 and 4x4 NoC mesh. Up to 11% reduction in power consumption and 20% reduction in APL has been observed as compared to other proposed mapping techniques.
Place, publisher, year, edition, pages
2010. 758-761 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-73484DOI: 10.1109/ICECS.2010.5724623ScopusID: 2-s2.0-79953077714ISBN: 978-142448157-6OAI: oai:DiVA.org:kth-73484DiVA: diva2:488928
2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010; Athens; 12 December 2010 through 15 December 2010
QC 201202082012-02-022012-02-022015-07-29Bibliographically approved