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A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip
University of Turku and Turku Centre for Computer Science (TUCS).
University of Turku and Turku Centre for Computer Science (TUCS).
University of Turku.
University of Turku and Turku Centre for Computer Science (TUCS).
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2011 (English)In: Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on, IEEE Computer Society, 2011, 454-462 p.Conference paper, Published paper (Refereed)
Abstract [en]

We present the partial virtual-channel sharing (PVS) NoC architecture which reduces the impact of fault on system performance and can also tolerate the faults on routing logic. A fault in one component makes the fault-free connected components out of use and this in turn leads to considerable performance degradation. Improving utilization of resources is a key to either enhance or sustain performance with minimal overheads in case of fault or overloading. In the proposed architecture autonomic virtual-channel buffer sharing is implemented. The runtime allocation of the buffers depends on incoming load and fault occurrence. This technique can be used in any NoC topology and for both 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate significant reduction in average packet latency compared to existing VC-based NoC architecture. Extensive quantitative simulation results for synthetic benchmarks are also carried out. Furthermore, the simulation results reveal that the PVS architecture improves the performance significantly under fault free conditions compared to other VC architectures.

Place, publisher, year, edition, pages
IEEE Computer Society, 2011. 454-462 p.
Series
International Symposium on Defect and Fault - Tolerance in VLSI Systems. Proceedings, ISSN 1550-5774 ; 2011
Keyword [en]
Fault tolerance, Networks-on-Chip (NoC), Resource utilization, Virtual channel sharing
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-73482DOI: 10.1109/DFT.2011.16ISI: 000299533900054Scopus ID: 2-s2.0-84855767361ISBN: 978-076954556-1 (print)OAI: oai:DiVA.org:kth-73482DiVA: diva2:488931
Conference
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011; Vancouver, BC; 3 October 2011 through 5 October 2011
Note

QC 20120220

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2015-07-29Bibliographically approved

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Rahmani, Amir-MuhammadTenhunen, Hannu
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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
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  • asciidoc
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