Change search
ReferencesLink to record
Permanent link

Direct link
Input-Output Selection Based Router for Networks-on-Chip
Show others and affiliations
2010 (English)In: IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, 92-97 p.Conference paper (Refereed)
Abstract [en]

In this paper, we propose a novel on-chip router architecture for avoiding congested areas in regular twodimensional on-chip networks. This architecture takes advantage of an efficient adaptive routing model based on the Hamiltonian path for both the multicast and unicast traffic. The output selection of the proposed architecture is based on the congestion condition of neighboring routers and the input selection is based on the Weighted Round Robin mechanism which allows packets to be serviced from each input port according to its congestion level The simulation results show that in multicast, unicast, and mixed traffic profiles the proposed model has lower average delays and lower average and peak power compared to previously proposed models.

Place, publisher, year, edition, pages
2010. 92-97 p.
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-73467DOI: 10.1109/ISVLSI.2010.76ScopusID: 2-s2.0-77957926962OAI: diva2:488962
IEEE Annual Symposium on VLSI, ISVLSI 2010. Lixouri, Kefalonia. 5 July 2010 - 7 July 2010

QC 20120208

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-09-01Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Tenhunen, Hannu
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 32 hits
ReferencesLink to record
Permanent link

Direct link