Input-Output Selection Based Router for Networks-on-Chip
2010 (English)In: IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, 92-97 p.Conference paper (Refereed)
In this paper, we propose a novel on-chip router architecture for avoiding congested areas in regular twodimensional on-chip networks. This architecture takes advantage of an efficient adaptive routing model based on the Hamiltonian path for both the multicast and unicast traffic. The output selection of the proposed architecture is based on the congestion condition of neighboring routers and the input selection is based on the Weighted Round Robin mechanism which allows packets to be serviced from each input port according to its congestion level The simulation results show that in multicast, unicast, and mixed traffic profiles the proposed model has lower average delays and lower average and peak power compared to previously proposed models.
Place, publisher, year, edition, pages
2010. 92-97 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-73467DOI: 10.1109/ISVLSI.2010.76ScopusID: 2-s2.0-77957926962OAI: oai:DiVA.org:kth-73467DiVA: diva2:488962
IEEE Annual Symposium on VLSI, ISVLSI 2010. Lixouri, Kefalonia. 5 July 2010 - 7 July 2010
QC 201202082012-02-022012-02-022016-09-01Bibliographically approved