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High-Performance TSV Architecture for 3-D ICs
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2010 (English)In: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, 467-468 p., 5572813Conference paper, Published paper (Refereed)
Abstract [en]

Three-dimensional integrated circuits (3-D ICs) outperform traditional planar ICs in terms of performance, packaging density, interconnection power consumption, and functionality. Since the performance of 3-D ICs employing Through Silicon Vias (TSVs) depends on vertical interlayer interconnects, in this paper we present a high-performance bus architecture for TSVs.

Place, publisher, year, edition, pages
2010. 467-468 p., 5572813
Keyword [en]
3-D ICs, Bus architecture, Packaging density, Power Consumption, Three dimensional integrated circuits, Through silicon vias
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-73465DOI: 10.1109/ISVLSI.2010.24Scopus ID: 2-s2.0-77957917264ISBN: 978-076954076-4 (print)OAI: oai:DiVA.org:kth-73465DiVA: diva2:488963
Conference
IEEE Annual Symposium on VLSI, ISVLSI 2010. Lixouri, Kefalonia. 5 July 2010 - 7 July 2010
Note

QC 20120208

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-07-22Bibliographically approved

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