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CMIT: A novel cluster-based topology for 3D stacked architectures
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2010 (English)In: IEEE 3D System Integration Conference 2010, 3DIC 2010, 2010Conference paper (Refereed)
Abstract [en]

Combining the benefits of 3D IC and Network-on-Chip (NoC) schemes, provides a significant performance gain for 3D stacked architectures. In recent years, Through-Silicon-Via (TSV), employed for inter-layer connectivity (vertical channel), has attracted a lot of interest since it enables faster and more power efficient inter-layer communication across multiple stacked layers. However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs. In this paper, we propose a novel stacked topology, named CMIT (Cluster Mesh Inter-layer Topology) for 3D architectures to reduce the area overhead of TSVs and power dissipation on each layer with minimal performance penalty. Experimental results with synthetic test cases demonstrate that the presented topology can save more than 75% of TSV area footprint and reduces more than 10% of power consumption with a negligible performance overhead.

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Engineering and Technology
URN: urn:nbn:se:kth:diva-73463DOI: 10.1109/3DIC.2010.5751452ScopusID: 2-s2.0-79955962345ISBN: 978-145770527-4OAI: diva2:488965
2nd IEEE International 3D System Integration Conference, 3DIC 2010. Munich, Germany 16 November 2010 - 18 November 2010

QC 20150708

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2015-07-08Bibliographically approved

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Tenhunen, Hannu
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