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A Low-Latency and Memory-Efficient On-chip Network
University of Turku, Finland.
University of Turku, Finland.
University of Turku, Finland.
University of Turku, Finland.
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2010 (English)In: NOCS 2010: The 4th ACM/IEEE International Symposium on Networks-on-Chip, 2010, 99-106 p., 5507556Conference paper, Published paper (Refereed)
Abstract [en]

Using multiple SDRAMs in MPSoCs and NoCs to increase memory parallelism is very common nowadays. In-order delivery, resource utilization, and latency are the most critical issues in such architectures. In this paper, we present a novel network interface architecture to cope with these issues efficiently. The proposed network interface exploits a resourceful reordering mechanism to handle the in-order delivery and to increase the resource utilization. A brilliant memory controller is efficiently integrated into this network interface to improve the memory utilization and reduce both memory and network latencies. In addition, to bring compatibility with existing IP cores the proposed network interface utilizes AXI transaction based protocol. Experimental results with synthetic test cases demonstrate that the proposed architecture gives significant improvements in average network latency (12%), average memory access latency (19%), and average memory utilization (22%).

Place, publisher, year, edition, pages
2010. 99-106 p., 5507556
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-73464DOI: 10.1109/NOCS.2010.19Scopus ID: 2-s2.0-77955098839OAI: oai:DiVA.org:kth-73464DiVA: diva2:488966
Conference
4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010. Grenoble. 3 May 2010 - 6 May 2010
Note

QC 20120208

Available from: 2012-02-02 Created: 2012-02-02 Last updated: 2016-09-01Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
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  • vancouver
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  • de-DE
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  • en-US
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  • nn-NO
  • nn-NB
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  • Other locale
More languages
Output format
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  • asciidoc
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