Memory-Efficient On-Chip Network With Adaptive Interfaces
2012 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 31, no 1, 146-159 p.Article in journal (Refereed) Published
To achieve higher memory bandwidth in network-based multiprocessor architectures, multiple dynamic random access memories can be accessed simultaneously. In such architectures, not only resource utilization and latency are the critical issues but also a reordering mechanism is required to deliver the response transactions of concurrent memory accesses in-order. In this paper, we present a memory-efficient on-chip network architecture to cope with these issues efficiently. Each node of the network is equipped with a novel network interface (NI) to deal with out-of-order delivery, and a priority-based router to decrease the network latency. The proposed NI exploits a streamlined reordering mechanism to handle the in-order delivery and utilizes the advance extensible interface transaction-based protocol to maintain compatibility with existing intellectual property cores. To improve the memory utilization and reduce the memory latency, an optimized memory controller is integrated in the presented NI. Experimental results with synthetic test cases demonstrate that the proposed on-chip network architecture provides significant improvements in average network latency (16%), average memory access latency (19%), and average memory utilization (22%).
Place, publisher, year, edition, pages
2012. Vol. 31, no 1, 146-159 p.
AXI transaction protocol, memory controller, network interface, networks-on-chip
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-73461DOI: 10.1109/TCAD.2011.2160348ISI: 000298327500014OAI: oai:DiVA.org:kth-73461DiVA: diva2:488967
QC 201202132012-02-022012-02-022013-01-22Bibliographically approved