High-performance on-chip network platform for memory-on-processor architectures
2011 (English)In: 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011, 5981509Conference paper (Refereed)
Three Dimensional Integrated Circuits (3D ICs) are emerging to improve existing Two Dimensional (2D) designs by providing smaller chip areas, higher performance and lower power consumption. Stacking memory layers on top of a multiprocessor layer (logic layer) is a potential solution to reduce wire delay and increase the bandwidth. To fully employ this capability, an efficient on-chip communication platform is required to be integrated in the logic layer. In this paper, we present an on-chip network platform for the logic layer utilizing an efficient network interface to exploit the potential bandwidth of stacked memory-on-processor architectures. Experimental results demonstrate that the platform equipped with the presented network interface increases the performance considerably.
Place, publisher, year, edition, pages
Memory Wall, Memory-on-Processor Architectures, Network-on-Chip, Three Dimension Integrated Circuit
IdentifiersURN: urn:nbn:se:kth:diva-73462DOI: 10.1109/ReCoSoC.2011.5981509ScopusID: 2-s2.0-80052586785ISBN: 978-145770642-4OAI: oai:DiVA.org:kth-73462DiVA: diva2:488968
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011. Montpellier. 20 June 2011 - 22 June 2011
QC 201202082012-02-022012-02-022016-07-22Bibliographically approved